1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a technique of suppressing the deterioration of a display quality.
2. Description of the Related Art
Up to now, liquid crystal display devices have been known in which a planar common electrode is formed on a passivation layer formed on a source electrode and a drain electrode configuring a TFT (thin film transistor) , an interlayer insulating film is formed on the common electrode, and a pixel electrode is formed on the interlayer insulating film (refer to JP 2010-181785 A).
A back channel region to be described later is present in an upper portion of a semiconductor layer (amorphous silicon layer (a-si layer)) which is located between the source electrode and the drain electrode, and formed on a gate electrode.
Hereinafter, a description will be given of a configuration of a TFT array in which a columnar spacer is arranged on each TFT with reference to FIGS. 8 and 9.
FIG. 8 is a plan view illustrating a main portion of a pixel in a conventional liquid crystal display device 100. FIG. 9 is a cross-sectional view taken along a line IX-IX′ of FIG. 8. In FIGS. 8 and 9, X, Y, and Z represent an X-axis, a Y-axis, and a Z-axis, respectively.
As illustrated in FIG. 9, a TFT array 101 includes a gate electrode 112, a gate insulating film 111, a semiconductor layer 109, a drain electrode 107, a source electrode 108, a passivation layer 103, and a common electrode 102.
The gate electrode 112 is formed on an insulating substrate not shown. The gate insulating film 111 is so formed as to cover the gate electrode 112.
The semiconductor layer 109 is formed on the gate insulating film 111, and at a position facing the gate electrode. The semiconductor layer 109 forms a back channel region 113 (hereinafter referred to simply as “channel region”) of the TFT, and, for example, is formed through a plasma CVD technique.
The drain electrode 107 and the source electrode 108 are formed on the semiconductor layer 109 so as to sandwich the channel region 113 therebetween.
In this case, as illustrated in FIG. 8, the drain electrode 107 is coupled to a video signal line (drain line) 104 extending in a Y-direction of FIG. 8. A video signal (gradation signal) from a driver circuit not shown is supplied to the video signal line 104. The source electrode 108 is coupled to a pixel electrode 117 (refer to FIG. 8).
Also, the gate electrode 112 is coupled to a scanning signal line (gate line) 105 extending in an X-direction of FIG. 8. A scanning signal is supplied from the driver circuit to the scanning signal line 105.
As illustrated in FIG. 8, a unit pixel is configured by a region surrounded by two adjacent video signal lines 104 and two adjacent scanning signal lines 105. A plurality of the unit pixels are arranged in a matrix along the video signal lines 104 and the scanning signal lines 105.
As illustrated in FIG. 9, the passivation layer 103 is formed above the drain electrode 107 and the source electrode 108 so as to cover the TFT constituted by the gate electrode 112, the drain electrode 107, and the source electrode 108.
The common electrode 102 is formed on the passivation layer 103 in a region except for an opening portion 114 which will be described later. In this case, the opening portion 114 has a region (which is a square region in this embodiment) surrounded by a boundary line indicated by reference numeral 106 of FIG. 8. The opening region is a region wider than at least the channel region 113 (refer to FIG. 9), which is provided for the purpose of preventing the back channel effect as will hereinafter be described.
A columnar spacer 110 for ensuring a region in which liquid crystal not shown is to be sealed is arranged above the channel region 113.
Incidentally, the back channel effect means that when a small back gate voltage is applied to the gate electrode 112 in a state where the TFT is off, a leakage current is allowed to flow into the drain electrode 107 and the source electrode 108 through the channel region 113.
A case in which the back gate voltage is developed in the state where the TFT is off is, for example, when positively charged impurity ions are put on the TFT. When the back channel effect occurs in the state where the TFT is off, electric charge held on the TFT used in each pixel of an LCD panel disappears, and so-called “whiting” occurs, resulting in such a problem that the display quality of the liquid crystal display device is deteriorated.
Under the circumstances, in order to prevent the back channel effect, the opening portion 114 is formed in a region corresponding to the channel region 113 within the region where the common electrode 102 is formed. The opening portion 114 is formed, and the impurity ions existing on the TFT are escaped from the opening portion 114, thereby making it possible to suppress the occurrence of the above-mentioned back gate voltage.
Incidentally, when an impact is exerted on the liquid crystal display panel from the external of the liquid crystal display device 100, the impact (force F in FIG. 9) is also transmitted to the columnar spacer 110. For example, when the impact is exerted in a direction perpendicular to the liquid crystal display panel (in a thickness direction of the TFT array 101 (hereinafter called “TFT thickness direction”) from the external of the liquid crystal display device 100, the force F acts on the columnar spacer 110 in the TFT thickness direction.
When the force F acts on the columnar spacer 110 in the TFT thickness direction, the columnar spacer 110 collides with the passivation layer 103. When the columnar spacer 110 collides with the passivation layer 103, a static electricity 115 occurs above the channel region 113.
Because the transistor characteristic of the TFT fluctuates due to the static electricity 115, color unevenness, smear, or misadjusted black level occurs in a display image of the liquid crystal display device 100. This leads to such a problem that the display quality of the liquid crystal display device 100 is deteriorated.